Virtually all semiconductor memory integrated circuits require the use of a sense amplifier to output stored data. The sense amplifier is a basic component for sensing the output voltage of a memory cell in response to signals on a bit-line. The sense amplifier senses logic levels representing a one or zero stored in the memory cell and amplifies the small voltage to complimentary metal-oxide semiconductor (CMOS) logical voltage levels.
As CMOS technology tends to become smaller, more dense, and faster over time, improvements in high-speed processor design have outpaced those of semiconductor memory, creating a bottleneck with respect to overall integrated circuit speed. As a result, CMOS technology development is experiencing diminishing returns and will continue down that path until memory speeds catch up to processing speeds.
Semiconductor memory designs are constrained by concerns over power consumption, reliability, and, of course, time. Read and write cycle times define a memory chip's speed. Specifically, read times are largely dictated by the speed at which the sense amplifier operates to provide CMOS level data. In the case of a double-ended differential sense amplifier, the latency of the sense amplifier rides on the speed at which it can recognize a voltage differential.
The general rule is that as voltage differential increases, the amplifier's reaction time decreases. The boundary on this rule is that while larger voltage differentials are achievable, yielding faster sense amplifier reaction, the voltages take longer to discharge. Once discharged, additional power is then required to recharge the circuit. Sense amplifiers are designed to strike a balance among sense amplifier reaction time, discharge time and power consumption.